Archive
2024
2023
2022
- VEDA: Best practices to use hybrid programming on the NEC SX-Aurora TSUBASA (12.11.2022)
- Keras Merge (09.11.2022)
- ACCELERATION OF NEURAL NETWORKS USING DEPTH - FIRST PROCESSING (30.08.2022)
- SOL: Reducing the Maintenance Overhead for Integrating Hardware Support into AI Frameworks (01.05.2022)
- SOL: Single middleware for optimized multi-architecture AI training and deployment (01.01.2022)
2021
- AVEO-VEDA: Hybrid Programming for the NEC Vector Engine (14.07.2021)
- Flynn’s reconciliation: Automating the register cache idiom for cross-accelerator programming (01.05.2021)
2020
- SOL: Transparent Neural Network Acceleration on NEC SX-Aurora TSUBASA (01.09.2020)
- SOL: Effortless Device Support for AI Frameworks without Source Code Changes (01.05.2020)
- SOL4VE: Running Deep Neural Networks on the NEC SX-Aurora Tsubasa (01.01.2020)
- SOL4VE: Bringing Deep Neural Networks to the NEC SX-Aurora TSUBASA (01.01.2020)
2018
- Detail-Preserving Pooling in Deep Networks (01.05.2018)
- BrainSlug: Transparent Acceleration of Deep Learning Through Depth-First Parallelism (01.05.2018)
- BrainSlug: Transparent Acceleration of Deep Learning Through Depth-First Parallelism (01.05.2018)
- Sol: Transparent Neural Network Acceleration Platform (01.01.2018)
2017
- Prospect for Knowledge in Survey Data: An Artificial Neural Network Sensitivity Analysis (01.01.2017)
- MATOG: Array Access Auto-Tuning (01.01.2017)
- GPU Array Access Auto-Tuning (01.01.2017)
2016
- Rapid, Detail-Preserving Image Downscaling (01.01.2016)
- Adaptive GPU Array Layout Auto-Tuning (01.01.2016)
2015
2014
2013
- Fast Dynamic Memory Allocator for Massively Parallel Architectures (01.01.2013)
- Construction of Ray-Tracing Acceleration Structures in an Out-of-Core Multi-GPU Environment (01.01.2013)