Nicolas Weber

Research Scientist

Research Interests

  • Auto-Tuning / Automated Performance Optimizations
  • High Performance Computing
  • GPU Computing
  • Artifical Intelligence / Machine Learning

About Me

I am Nicolas Weber, Senior Researcher in the Intelligent Software Systems Group of the NEC Laboratories Europe. Before, I was Ph.D. student at the Graphics, Capture and Massively Parallel Computing Group at TU Darmstadt. My Ph.D. topic was on automated performance optimizations for GPU array access. In my research I mainly focus on performance optimizations for GPU based applications in the High Performance Computing (HPC) and Artificial Intelligence (AI) applications.

Curriculum Vitae

Senior Researcher   

since 07/2019
Intelligent Software Systems Group, NEC Laboratories Europe

Research Scientist   

09/2017 - 06/2019
Systems and Machine Learning Group, NEC Laboratories Europe

Research Assistant   

05/2013 - 05/2017
Graphics, Capture and Massively Parallel Computing Group, TU Darmstadt

Publications

SOL: Effortless Device Support for AI Frameworks without Source Code Changes   

2020 - Nicolas Weber and Felipe Huici
HPML'20

BrainSlug: Transparent Acceleration of Deep Learning Through Depth-First Parallelism   

2018 - Nicolas Weber, Florian Schmidt, Mathias Niepert and Felipe Huici
arXiv

Detail-Preserving Pooling in Deep Networks   

2018 - Faraz Saeedan, Nicolas Weber, Michael Goesele and Stefan Roth
Conference on Computer Vision and Pattern Recognition (CVPR)

Prospect for Knowledge in Survey Data: An Artificial Neural Network Sensitivity Analysis   

2017 - Patrick Weber, Nicolas Weber, Michael Goesele and Rüdiger Kabst
Social Science Computer Review

GPU Array Access Auto-Tuning   

2017 - Nicolas Weber
Ph.D. Thesis, TU Darmstadt

MATOG: Array Access Auto-Tuning   

2017 - Nicolas Weber and Michael Goesele
ACM Transactions on Architecture and Code Optimization (TACO)

Rapid, Detail-Preserving Image Downscaling   

2016 - Nicolas Weber, Michael Waechter, Sandra C. Amend, Stefan Guthe and Michael Goesele
ACM Transactions on Graphics (TOG), SIGGRAPH Asia, Macao, PR China

Adaptive GPU Array Layout Auto-Tuning   

2016 - Nicolas Weber and Michael Goesele
Software Engineering Methods for Parallel and High Performance Applications (SEM4HPC), Kyoto, Japan

Guided Profiling for Auto-Tuning Array Layouts on GPUs   

2015 - Nicolas Weber, Sandra C. Amend and Michael Goesele
Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS), Austin, TX, USA

Auto-Tuning Complex Array Layouts for GPUs   

2014 - Nicolas Weber and Michael Goesele
Eurographics Symposium on Parallel Graphics and Visualization (EGPGV), Swansea, United Kingdom

Construction of Ray-Tracing Acceleration Structures in an Out-of-Core Multi-GPU Environment   

2013 - Nicolas Weber
M.Sc. Thesis, TU Darmstadt

Fast Dynamic Memory Allocator for Massively Parallel Architectures   

2013 - Sven Widmer, Dominik Wodniok, Nicolas Weber and Michael Goesele
Workshop on General Purpose Processor Using Graphics Processing Units (GPGPU), Houston, TX, USA

Transportprotokoll und Systemdienste für den Controller Area Network Bus   

2010 - Nicolas Weber
B.Sc. Thesis, TU Darmstadt

Posters

Sol: Transparent Neural Network Acceleration Platform   

2018 - Nicolas Weber
Supercomputing (SC), Dallas, TX, USA

Talks

Integration of NEC SX-Aurora into AI Frameworks   

2019 - Nicolas Weber, Erich Focht
Workshop on Sustained Simulation, Stuttgart, Germany

Sol: Transparent Neural Network Acceleration   

2019 - Nicolas Weber
Supercomputing Frontiers Europe, Warsaw, Poland

BrainSlug: Transparent Acceleration of Deep Learning Through Depth-First Parallelism   

2018 - Nicolas Weber, Florian Schmidt, Mathias Niepert and Felipe Huici
International Workshop on Embedded and Mobile Deep Learning, Munich, Germany

Reviewer

JRTIP: Journal of Real-Time Image Processing   

2014, 2017-2020

JSA: Journal of Systems Architecture   

2018

VMV: Symposium on Vision, Modeling, and Visualization   

2016

Projects

SOL - Transparent Acceleration of Neural Networks.
Detail-Preserving Pooling in Deep Networks - Alternative pooling layer for deep neural networks based on DPID.
MATOG - Array access performance auto-tuner for CUDA.
Detail Preserving Image Downscaling - Alternative perceptual inspired image downscaling algorithm.
FDGMalloc - Fast dynamic memory allocator for CUDA.
Fujitsu FX16 CAN Library - CAN network protocol library for Fujitsu FX16 microcontroller.