About me

I am Nicolas Weber, research engineer in the Intelligent Software Systems Group at the NEC Laboratories Europe. Before, I was PhD student in the Graphics, Capture and Massively Parallel Computing Group at TU Darmstadt supervised by Prof. Michael Goesele and Associate of the Graduate School of Computational Engineering at TU Darmstadt.

My main research interests are the automated optimization of code running on accelerator hardware, especially for Scientific and High Performance Computing, Biomedical and Artificial Intelligence applications.

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AUTOMATIC LOW LEVEL OPERATOR LOOP GENERATON, PARALLELIZATION AND VECTORIZATION FOR TENSOR COMPUTATIONS

A method is provided for transforming a high-level language representation of a tensor computation graph into a low level language. The method includes assigning a tensor shape and a loop primitive. The method also includes generating, from the tensor computation graph and the assigned loop primitives, an initial loop structure. The method further includes positioning the layers of the tensor computation graph within a nested loop structure to provide a final loop structure, collapsing loops in the final loop structure, and mapping the collapsed loops to hardware components configured to execute the collapsed loops. The method can be applied to artificial intelligence (AI) and machine learning (ML) use cases for improved optimization of neural networks including compilation optimization for improving performance of simulations such as medical simulations, healthcare simulations, weather simulations, and/or simulations related to other complex systems, which can also support decision making.

DYNAMIC PATHWAYS FOR ARTIFICIAL INTELLIGENCE AND TENSOR COMPUTATION GRAPHS

A method for optimizing control flow in compiled computation graphs includes defining an intermediate representation (IR) of a computation graph, the computation graph IR including a main computation graph having at least one control flow primitive layer node pointing to one or more control flow sub-graph nodes. Fusable layer nodes of the main computation graph are identified and removed from the main computation graph, and the removed fusable layer nodes are duplicated into each of the one or more control flow sub-graph nodes. The method can be applied to machine learning frameworks, for example, for scientific computations such as in medical AI.

PREPROCESSING CODE USING LARGE LANGUAGE MODELS FOR PERFORMANCE PORTABILITY

A computer-implemented, machine learning method for preprocessing code for performance portability includes extracting performance critical code segments from an application and obtaining input data. Ground truth data is generated based on the input data and the application. Original code of the application is transpiled using a large language model (LLM) into a tensor computation language (TCL) candidate. Correctness of an implementation of the TCL candidate is verified using the ground truth data. The method has applications including, but not limited to, use cases in medical/healthcare, and other artificial intelligence applications for preprocessing and optimizing code for performance portability. The method can also support decision making and could be implemented with machine learning.

Facilitate high-performance hardware integration into AI Frameworks with the NEC SOL AI compiler

AI development has become increasingly driven by powerful frameworks like PyTorch and TensorFlow, supported by major tech companies. However, the rapid release cycles of these frameworks – every 3-6 months – pose a challenge for new hardware vendors. They struggle to develop the necessary AI functionality and keep pace with frequent updates. In this talk, we introduce NEC’s SOL AI compiler, which seamlessly integrates with PyTorch, TensorFlow, ONNX, Numpy, and soon JAX. SOL provides a unified compiler engine for these frameworks, supporting both inference and training, while also enabling model export to standalone libraries with minimal dependencies. Designed for device-agnostic support and ease of maintenance, SOL requires no specific compiler support (e.g., OpenCL, SyCL, OpenMP, Triton, MLIR, …) but can generate device tailored code with minimal coding effort. We will present SOL’s key concepts and its device-agnostic design in this talk.

Higher-Rank Irreducible Cartesian Tensors for Equivariant Message Passing

The ability to perform fast and accurate atomistic simulations is crucial for advancing the chemical sciences. By learning from high-quality data, machine-learned interatomic potentials achieve accuracy on par with ab initio and first-principles methods at a fraction of their computational cost. The success of machine-learned interatomic potentials arises from integrating inductive biases such as equivariance to group actions on an atomic system, e.g., equivariance to rotations and reflections. In particular, the field has notably advanced with the emergence of equivariant message passing. Most of these models represent an atomic system using spherical tensors, tensor products of which require complicated numerical coefficients and can be computationally demanding. Cartesian tensors offer a promising alternative, though state-of-the-art methods lack flexibility in message-passing mechanisms, restricting their architectures and expressive power. This work explores higher-rank irreducible Cartesian tensors to address these limitations. We integrate irreducible Cartesian tensor products into message-passing neural networks and prove the equivariance and traceless property of the resulting layers. Through empirical evaluations on various benchmark data sets, we consistently observe on-par or better performance than that of state-of-the-art spherical and Cartesian models.

arXiv, Poster

COMBINATION OF MULTIPLE DATA PROCSSING AND MACHINE LEARNING FRAMEWORKS FOR A TARGET HARDWARE

A method for combining multiple different data processing, artificial intelligence and/or machine learning frameworks for execution by a target hardware includes extracting one or more computation graphs from each of the different frameworks. The computation graphs are combined into a fused computation graph. Memcopy operations are removed at edges between the computation graphs of the different frameworks. Memory spaces for computations in the fused computation graph are remapped to memory spaces of the target hardware.

FULL ASYNCHRONOUS EXECUTION QUEUE FOR ACCELERATOR HARDWARE

A method for providing an asynchronous execution queue for accelerator hardware includes replacing a malloc operation in an execution queue to be sent to an accelerator with an asynchronous malloc operation that returns a unique reference pointer. Execution of the asynchronous malloc operation in the execution queue by the accelerator allocates a requested memory size and adds an entry to a look-up table accessible by the accelerator that maps the reference pointer to a corresponding memory address.

VEDA: Best practices to use hybrid programming on the NEC SX-Aurora TSUBASA

The Vector Engine Driver API (VEDA) was developed to enable easy porting of existing CUDA applications to NEC’s SX-Aurora TSUBASA. While the API enables a smooth transition between the different architectures, there are unique features that require special attention, to achieve optimal performance.

In this article we present multiple methods to improve your code. First, we explain how to use C++ function overloading and templates. Second, we show how to make best use of the unique features of VEDAdeviceptrs. Third, we explain our improvements for VEDA’s memset and memcopy operations, that can also improve your own code.

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