SOL: Reducing the Maintenance Overhead for Integrating Hardware Support into AI Frameworks

The increased interest in Artificial Intelligence (AI) raised the need for highly optimized and sophisticated AI frameworks. Starting with the Lua-based Torch many frameworks have emerged over time, such as Theano, Caffe, Chainer, CNTK, MxNet, PyTorch, DL4J, or TensorFlow.

All of these provide a high level scripting API that allows users to easily design neural networks and run these on various kinds of hardware. What the user usually does not see is the high effort put into these frameworks to provide peak execution performance.

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SOL: Single middleware for optimized multi-architecture AI training and deployment

NEC User Group Meeting

AVEO-VEDA: Hybrid Programming for the NEC Vector Engine

Hybrid programming is a state of the art method for incorporating compute accelerators such as GPUs or vector processors into applications that run on a host system. The main reason for hybrid programming is that compute accelerators are well suited for compute and memory heavy tasks but perform poorly in control flow dominated code sections. Therefore latter are usually executed on CPUs while the compute heavy parts are offloaded to accelerators. This article introduces the low-level AVEO and high-level VEDA programming APIs for programming the NEC SX-Aurora TSUBASA, also called Vector Engine (VE).

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Flynn’s reconciliation: Automating the register cache idiom for cross-accelerator programming

ACM Transactions on Architecture and Code Optimization (TACO)

SOL: Effortless Device Support for AI Frameworks without Source Code Changes

High Performance Machine Learning (HPML)‘20

SOL4VE: Bringing Deep Neural Networks to the NEC SX-Aurora TSUBASA

NEC User Group Meeting

SOL4VE: Running Deep Neural Networks on the NEC SX-Aurora Tsubasa